On Thu, May 26, 2016 at 12:41:31PM -0400, Rhyland Klein wrote: > From: Andrew Bresticker <abrestic@xxxxxxxxxxxx> > > Move the UTMIPLL initialization code form clk-tegra<chip>.c files into > clk-pll.c. UTMIPLL was being configured and set in HW control right > after registration. However, when the clock init_table is processed and > child clks of PLLU are enabled, it will call in and enable PLLU as > well, and initiate SW enabling sequence even though PLLU is already in > HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. > > Doing the initialization once during pllu_enable means we configure it > properly into HW control. > > A side effect of the commonization/localization of the UTMIPLL init > code, is that it corrects some errors that were present for earlier > generations. For instance, in clk-tegra124.c, it used to have: > > define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) > > when the correct shift to use is present in the new version: > > define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) > > which matches the Tegra124 TRM register definition. > > Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx> > > [rklein: Merged in some later fixes for potential deadlocks] > > Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx> > --- > v5: > - Initialized flags to 0 to avoid harmless spinlock warnings > > v4: > - Re-added examples in patch description > > v3: > - Flushed out description to describe this patch. > > drivers/clk/tegra/clk-pll.c | 484 +++++++++++++++++++++++++++++++++++++++ > drivers/clk/tegra/clk-tegra114.c | 155 +------------ > drivers/clk/tegra/clk-tegra124.c | 156 +------------ > drivers/clk/tegra/clk-tegra210.c | 182 +-------------- > drivers/clk/tegra/clk-tegra30.c | 113 +-------- > drivers/clk/tegra/clk.h | 17 ++ > 6 files changed, 510 insertions(+), 597 deletions(-) Applied, thanks. Thierry
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