On 3/14/2016 12:05 PM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Thu, Mar 10, 2016 at 02:38:05PM -0500, Rhyland Klein wrote: >> From: Bill Huang <bilhuang@xxxxxxxxxx> >> >> Add some SLCG (Second Level Clock Gating) override clocks to control >> gating and un-gating their logics. >> >> Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx> >> Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx> >> --- >> drivers/clk/tegra/clk-id.h | 16 ++++++ >> drivers/clk/tegra/clk-tegra210.c | 91 ++++++++++++++++++++++++++++++++ >> include/dt-bindings/clock/tegra210-car.h | 32 +++++------ >> 3 files changed, 123 insertions(+), 16 deletions(-) > > There's no rationale given here about why we need this. What will these > second level clock gates be used for? Why do we need these (seemingly) > duplicate clock entries. > These are going to be used in the to-be posted patchset around powergating. As of now they are unused, which is why I hadn't added them previously. I just wanted to try to get this dependency in before the powergate series was posted. -rhyland -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
