On Thu, Mar 10, 2016 at 02:38:05PM -0500, Rhyland Klein wrote: > From: Bill Huang <bilhuang@xxxxxxxxxx> > > Add some SLCG (Second Level Clock Gating) override clocks to control > gating and un-gating their logics. > > Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx> > Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx> > --- > drivers/clk/tegra/clk-id.h | 16 ++++++ > drivers/clk/tegra/clk-tegra210.c | 91 ++++++++++++++++++++++++++++++++ > include/dt-bindings/clock/tegra210-car.h | 32 +++++------ > 3 files changed, 123 insertions(+), 16 deletions(-) There's no rationale given here about why we need this. What will these second level clock gates be used for? Why do we need these (seemingly) duplicate clock entries. Thierry
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