On 02/24/2016 01:04 AM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Feb 23, 2016 at 03:25:54PM +0900, Alexandre Courbot wrote:
The default DMA mask covers a 32 bits address range, but tegradrm can
address more than that. Set the DMA mask to the actual addressable range
to avoid the use of unneeded bounce buffers.
Signed-off-by: Alexandre Courbot <acourbot@xxxxxxxxxx>
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Thierry, I am not absolutely sure whether the size is correct and applies
to all Tegra generations - please let me know if this needs to be
reworked.
drivers/gpu/drm/tegra/drm.c | 1 +
1 file changed, 1 insertion(+)
This kind of depends on whether or not the device is behind an IOMMU. If
it is, then the IOMMU DMA MASK would apply, which can be derived from
the number of address bits that the IOMMU can handle. The SMMU supports
32 address bits on Tegra30 and Tegra114, 34 address bits on more recent
generations.
I think for now it's safer to leave the DMA mask at the default (32 bit)
to avoid the need to distinguish between IOMMU and non-IOMMU devices.
Leaving it that way makes it (almost) impossible to import buffers on
TX1. Patch 1 sets the DMA ops to swiotlb, so at least after this we
actually try to import the buffer. However, any page that is higher than
the 32 bits range will be bounced. If you are lucky, you won't notice it
(even though I don't think it is acceptable to bounce data to be
displayed), but most of the time the swiotlb bounce area will run full
and import will fail with the following message:
drm drm: swiotlb buffer is full (sz: 294912 bytes)
So we should really try and fix this. The issue is, how do you detect
whether you are behind a IOMMU? The DCs have an iommus property, but the
drm device (which does the importing) does not. And when we import a
buffer into tegradrm, nothing guarantees that it is for display. So far
I cannot think of a better heuristics than "assume 32 bits on < t124 and
34 bits afterwards".
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