On Tue, Feb 23, 2016 at 08:18:26AM -0800, Terje Bergstrom wrote: > > > On 02/23/2016 08:04 AM, Thierry Reding wrote: > >* PGP Signed by an unknown key > > On Tue, Feb 23, 2016 at 03:25:54PM > >+0900, Alexandre Courbot wrote: > >> The default DMA mask covers a 32 bits address range, but tegradrm >> can > address more than that. Set the DMA mask to the actual >> addressable range > to avoid the use of unneeded bounce buffers. >> >> Signed-off-by: Alexandre > Courbot <acourbot@xxxxxxxxxx> --- Thierry, >> I am not absolutely sure > whether the size is correct and applies to >> all Tegra generations - please > let me know if this needs to be >> reworked. >> >> > drivers/gpu/drm/tegra/drm.c | 1 + 1 file changed, 1 insertion(+) > > This > kind of depends on whether or not the device is behind an IOMMU. > If it is, > then the IOMMU DMA MASK would apply, which can be derived > from the number > of address bits that the IOMMU can handle. The SMMU > supports 32 address > bits on Tegra30 and Tegra114, 34 address bits on > more recent generations. > > > I think for now it's safer to leave the DMA mask at the default (32 > > bit) to avoid the need to distinguish between IOMMU and non-IOMMU > devices. > > The GPUs after Tegra114 can choose per access whether they're using IOMMU > or not. The interface is 34 bits wide, so the physical addresses can be 34 > bits. > IOMMU addresses are limited by Tegra SMMU to 32-bit for gk20a. gm20b can use > 34-bit if SMMU is configured to combine four ASIDs together. This particular patch sets up the DMA mask for the display engines. But yes, most of the above holds true for that case as well, except that as far as I know there is no mechanism to have the display engines choose per access, whether or not to use the SMMU. Thierry
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