Re: [PATCH] clk: tegra124: Add init data for dsi lp clocks

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On Wed, Oct 01, 2014 at 12:40:41PM -0400, Sean Paul wrote:
> Set the parent of the dsi lp clocks to pll_p and the rate
> to 68MHz. The default parent is clk_m and rate is 12MHz, this
> is too slow to receive data from the peripheral.
> 
> Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
> will suffice.
> 

Looks good. I will take this for the next merge.

Cheers,

Peter.
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