On 10/31/2013 11:46 AM, Mark Rutland wrote: > On Thu, Oct 31, 2013 at 08:19:42AM +0000, Hiroshi Doyu wrote: >> Stephen Warren <swarren@xxxxxxxxxxxxx> wrote @ Wed, 30 Oct 2013 23:48:38 +0100: >> >>> On 10/18/2013 04:26 AM, Hiroshi Doyu wrote: >>>> Create a header file to define the swgroup IDs used by the IOMMU(SMMU) >>>> binding. "swgroups" is a group of H/W clients which Tegra SoCs >>>> support. This unique ID can be used to calculate MC_SMMU_<swgroup >>>> name>_ASID_0 register offset and MC_<swgroup name>_HOTRESET_*_0 >>>> register bit. This will allow the same header to be used by both >>>> device tree files, and drivers implementing this binding, which >>>> guarantees that the two stay in sync. This also makes device trees >>>> more readable by using names instead of magic numbers. >>> >>>> diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h >>> >>>> +#define TEGRA_SWGROUP_PPCS2 32 /* 0xab0 */ >>>> + >>>> +#define TEGRA_SWGROUP_BIT(x) (1ULL << TEGRA_SWGROUP_##x) >>> >>> Isn't the DT match all 32-bit, such that the ULL suffix does nothing, >> >> For the future Tegra SoC, the number of HWA grows a bit more, and it's >> supposed that "64" would be enough. > > Does DTC accept 64-bit values as-is? I recall DTC shouting at me in the past, > and having to split values across two u32 cells (i.e. <0xffffffff 0xffffffff> > rather than <0xffffffffffffffff>). Yes, you need to explicitly split the value across two cells in DT, since cells are 32-bit. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
