Calculate PLL_D parameters in a dynamically instead of using a fixed
table. This allows TegraDRM to drive outputs with CVT compliant modes.
Signed-off-by: Lucas Stach <dev@xxxxxxxxxx>
---
Maybe we can generalize this a bit and reuse this for other PLLs. But
for now the calculation is specific to PLL_D. To make this useable for
other PLLs we need to push cpcon and valid P values into the structure
that defines a PLL.
---
arch/arm/mach-tegra/tegra20_clocks.c | 88 +++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20_clocks.h | 1 +
arch/arm/mach-tegra/tegra20_clocks_data.c | 28 +---------
3 Dateien geändert, 91 Zeilen hinzugefügt(+), 26 Zeilen entfernt(-)
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 4eb6bc8..04b0ff59 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -894,6 +894,94 @@ struct clk_ops tegra_plle_ops = {
.round_rate = tegra20_pll_clk_round_rate,
};
+static int tegra20_plld_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long input_rate = parent_rate;
+ u64 n = 0;
+ int m_max, m_min, m = 0;
+ u32 val, rem = 0;
+ u8 cpcon = 0;
+
+ m_max = input_rate / c->u.pll.cf_min;
+ m_min = (input_rate / c->u.pll.cf_max) + 1;
+
+ for (m = m_min; m <= m_max; m++) {
+ n = (u64)rate * m;
+ rem = do_div(n, input_rate);
+ if (!rem)
+ break;
+ }
+
+ if (rem)
+ return -EINVAL;
+
+ c->mul = n;
+ c->div = n;
+
+ val = clk_readl(c->reg + PLL_BASE);
+ val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+ PLL_BASE_DIVM_MASK);
+ val |= (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT);
+ clk_writel(val, c->reg + PLL_BASE);
+
+ if (n <= 50)
+ cpcon = 2;
+ else if (n <= 300)
+ cpcon = 4;
+ else if (n <= 600)
+ cpcon = 8;
+ else if (n <= 1000)
+ cpcon = 12;
+
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val &= ~PLL_MISC_CPCON_MASK;
+ val |= cpcon << PLL_MISC_CPCON_SHIFT;
+ clk_writel(val, c->reg + PLL_MISC(c));
+
+
+ if (c->state == ON)
+ tegra20_pll_clk_enable(hw);
+
+ return 0;
+}
+
+static long tegra20_plld_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long input_rate = *prate;
+ u64 n;
+ u32 rem;
+ int m_max, m_min, m;
+
+ if (rate < c->u.pll.vco_min || rate > c->u.pll.vco_max)
+ return -EINVAL;
+
+ m_max = input_rate / c->u.pll.cf_min;
+ m_min = (input_rate / c->u.pll.cf_max) + 1;
+
+ /* check if we can find an matching integer N */
+ for (m = m_min; m <= m_max; m++) {
+ n = (u64)rate * m;
+ rem = do_div(n, input_rate);
+ if (!rem)
+ return rate;
+ }
+
+ return -EINVAL;
+}
+
+struct clk_ops tegra_plld_ops = {
+ .is_enabled = tegra20_pll_clk_is_enabled,
+ .enable = tegra20_pll_clk_enable,
+ .disable = tegra20_pll_clk_disable,
+ .set_rate = tegra20_plld_clk_set_rate,
+ .recalc_rate = tegra20_pll_clk_recalc_rate,
+ .round_rate = tegra20_plld_clk_round_rate,
+};
+
/* Clock divider ops */
static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
{
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
index 8bfd31b..b7bfe87 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -21,6 +21,7 @@ extern struct clk_ops tegra_clk_32k_ops;
extern struct clk_ops tegra_pll_ops;
extern struct clk_ops tegra_clk_m_ops;
extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
extern struct clk_ops tegra_pllx_ops;
extern struct clk_ops tegra_plle_ops;
extern struct clk_ops tegra_clk_double_ops;
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index a23a073..5a190ec 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -240,33 +240,9 @@ DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
tegra_pll_div_ops, pll_a, 0);
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 1, 4},
- { 13000000, 216000000, 216, 13, 1, 4},
- { 19200000, 216000000, 135, 12, 1, 3},
- { 26000000, 216000000, 216, 26, 1, 4},
-
- { 12000000, 297000000, 99, 4, 1, 4 },
- { 12000000, 339000000, 113, 4, 1, 4 },
-
- { 12000000, 594000000, 594, 12, 1, 8},
- { 13000000, 594000000, 594, 13, 1, 8},
- { 19200000, 594000000, 495, 16, 1, 8},
- { 26000000, 594000000, 594, 26, 1, 8},
-
- { 12000000, 616000000, 616, 12, 1, 8},
-
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
-
- { 0, 0, 0, 0, 0, 0 },
-};
-
DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
- 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
- 1000, tegra_pll_ops, 0, clk_m);
+ 1000000, 6000000, 40000000, 1000000000, NULL,
+ 1000, tegra_plld_ops, 0, clk_m);
DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
--
1.7.11.7
--
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