Re: [PATCH v2 2/2] tty/serial: Fix break handling for PORT_TEGRA

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On Tue, 17 May 2011 16:12:37 -0600
Stephen Warren <swarren@xxxxxxxxxx> wrote:

> When a break is received, Tegra's UART apparently fills the FIFO with
> 0 bytes. These must be drained so that they aren't interpreted as actual
> data received. This allows e.g. MAGIC_SYSRQ to work on Tegra's UARTs.
> 
> v2: Added FIXME comment to clear_rx_fifo

Acked-by: Alan Cox <alan@xxxxxxxxxxxxxxx>
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