Mark Brown wrote:
>
> On Fri, Dec 17, 2010 at 02:41:29PM -0700, Stephen Warren wrote:
> > Signed-off-by: Stephen Warren <swarren@xxxxxxxxxx>
>
> So, I actually have a one of these... If I can figure out how to get a
> useful kernel onto it I should be able to boot and test it.
That's be great. I did look at a sine wave on a 'scope, and there's a heck
of a lot of random or high-frequency noise on it...
> > ... lots of clk_set_rate etc.
> > ...
> > + err = snd_soc_dai_set_sysclk(codec_dai, 0, bitclock, SND_SOC_CLOCK_IN);
> > + if (err < 0) {
> > + pr_err(PREFIX "codec_dai clock not set\n");
> > + return err;
> > + }
>
> > + err = snd_soc_dai_set_sysclk(cpu_dai, 0, bitclock, SND_SOC_CLOCK_IN);
> > + if (err < 0) {
> > + pr_err(PREFIX "cpu_dai clock not set\n");
> > + return err;
> > + }
>
> Ah, this isn't bitclock, it's MCLK for the CODEC...
Ah. Perhaps that would explain some of the issues.
The clock fiddling above configures the I2S bit clock. This is fed out the
DAP1_SCLK pin of Tegra and into the BCLK pin of the codec.
The I2S driver then divides this down to generate the I2S LR clock.
We need to pick different frequencies for BCLK, because there's no frequency
within Tegra's clock limits (for pll_a, the root of the audio clock tree) that
is a common multiple of the bit clocks for all sample rates from 8000 to
96000Hz.
The codec's MCLK pin is driven by Tegra's DAP_MCLK1 pin. That is at a fixed
26MHz frequency.
Should I be passing the 26MHz fixed MCLK not I2S BCLK frequency to
snd_soc_dai_set_sysclk(codec_dai)?
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