Hi Jacopo, Thank you for the patch. On Fri, Feb 18, 2022 at 07:34:18PM +0100, Jacopo Mondi wrote: > Bits 13 and 12 of the ISP_CONFIGn register configure the PIXEL_MODE > which specifies the sampling size, in pixel component units, on the > CSI-2 output data interface when data are transferred to memory. > > The register description in the chip manual specifies that DUAL mode > should be used for YUV422 data. > > Signed-off-by: Jacopo Mondi <jacopo@xxxxxxxxxx> > Signed-off-by: Xavier Roumegue <xavier.roumegue@xxxxxxxxxxx> > --- > drivers/media/platform/imx/imx-mipi-csis.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/imx/imx-mipi-csis.c b/drivers/media/platform/imx/imx-mipi-csis.c > index 3e7efcf43a5f..86e7ea3713d9 100644 > --- a/drivers/media/platform/imx/imx-mipi-csis.c > +++ b/drivers/media/platform/imx/imx-mipi-csis.c > @@ -173,6 +173,7 @@ > #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) > #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) > #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ > +#define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) > #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) > #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) > #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) > @@ -506,7 +507,13 @@ static void __mipi_csis_set_format(struct csi_state *state) > > /* Color format */ > val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0)); > - val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK); > + val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK > + | MIPI_CSIS_ISPCFG_PIXEL_MASK); > + Let's add some more information here too: /* * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample * (referred to in the documentation as single and dual pixel modes * respectively, although the 8-bit mode transfers half a pixel per * clock sample and the 16-bit mode one pixel). While both mode work * when the CSIS is connected to a receiver that supports either option, * single pixel mode requires clock rates twice as high. As all SoCs * that integrate the CSIS can operate in 16-bit bit mode, and some do * not support 8-bit mode (this is the case of the i.MX8MP), use dual * pixel mode unconditionally. */ With this, Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > + /* TODO: Verify which other formats require DUAL (or QUAD) modes. */ I expect that at least RAW8 could benefit from dual mode too. While the i.MX8MM reference manual states that dual mode can also be used for RAW10 and RAW12, I think the CSI bridge has a 16-bit input bus, so this may not be possible (I could be wrong). > + if (state->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) > + val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; > + > val |= MIPI_CSIS_ISPCFG_FMT(state->csis_fmt->data_type); > mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val); > -- Regards, Laurent Pinchart
