Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

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On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> wrote:
> >
> > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > Hi all,
> > >
> > > This patch series add minimal change to provide mt7621 resets properly
> > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > controller of the SoC and is already providing clocks to the rest of
> > > the world.
> > >
> > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > hardware with software seems to define and add related reset code to the
> > > already mainlined clock driver.
> > >
> > > After this changes, we can get rid of the useless reset controller node
> > > in the device tree and use system controller node instead where the property
> > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > been updated with the new property accordly.
> > >
> > > This series also provide a bindings include header where all related
> > > reset bits for the MT7621 SoC are defined.
> > >
> > > Also, please take a look to this review [0] to understand better motivation
> > > for this series.
> > >
> > > Regarding the way of merging this:
> > >  - I'd like patches 1 and 4 which are related going through staging tree.
> >
> > Patches 1 and 4 now in the staging tree, thanks.
> 
> Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> also a dependency... Can we get all of them through the same tree,
> then? I am ok with both CLK or staging trees.

That's fine with me if they all go through the CLK tree, but there will
be a merge issue that I already fixed up in my tree.  If you want me to
drop them, just let me know.

thanks,

greg k-h




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