On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote: > Hi all, > > This patch series add minimal change to provide mt7621 resets properly > defining them in the 'mediatek,mt7621-sysc' node which is the system > controller of the SoC and is already providing clocks to the rest of > the world. > > There is shared architecture code for all ralink platforms in 'reset.c' > file located in 'arch/mips/ralink' but the correct thing to do to align > hardware with software seems to define and add related reset code to the > already mainlined clock driver. > > After this changes, we can get rid of the useless reset controller node > in the device tree and use system controller node instead where the property > '#reset-cells' has been added. Binding documentation for this nodeq has > been updated with the new property accordly. > > This series also provide a bindings include header where all related > reset bits for the MT7621 SoC are defined. > > Also, please take a look to this review [0] to understand better motivation > for this series. > > Regarding the way of merging this: > - I'd like patches 1 and 4 which are related going through staging tree. Patches 1 and 4 now in the staging tree, thanks. greg k-h
