Re: KSZ8795 not detected at start to boot from NFS

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi Jörg, all,

On 05/01/2025 18:08, Andrew Lunn wrote:
On Sun, Jan 05, 2025 at 05:33:38PM +0100, Jörg Sommer wrote:
Hi everyone,

I've added you to the list of recipients, because you where somehow involved
in changes of the KSZ-SPI switch code.

We are debating the SPI mode setting for the microchip ksz8795 and ksz9477
and possibly others. Since the commit
8c4599f49841dd663402ec52325dc2233add1d32 the SPI mode gets fixed to mode 3
in the code. But at least my ksz8795 works also with mode 0 and shows better
initialization behaviour with mode 0.

The big question is: can both (or all ksz) chips work with both modes?
Should this setting stay in code or moved to the device tree?

The specs are here, but I found no evidence about the supported/recommended
SPI modes:

https://ww1.microchip.com/downloads/en/DeviceDoc/KSZ9563R-Data-Sheet-DS00002419D.pdf

From this KSZ9563 datasheet it is quite clear from Figure 6-9 that it requires mode 0, for KSZ8794 (which I have and can test) Figure 7-8 [1] also indicates mode 0. Note however that older KSZ8794 datasheets (revision DS00002134A from 2016, can upload if needed) rather indicate a mode 3, which is a hint to me that indeed both modes were once supported. Appendix A from [1] states that in 2021 the SPI Timing images and parameters have been updated. No further information there but your experience and the datasheet update seem to indicate mode 0 has better support.

My SPI peripheral (and KSZ8 driver) is configured for mode 3 I see but the frequency is set to 10 MHz while the max is 50 MHz. From experience with other SPI devices I know that with higher frequencies the timing parameters (setup and hold times, mode) become more important, what frequency do you have configured Jörg? I'm asking because I don't experience the issue you have.

[1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ8794CNX-Data-Sheet-DS00002134.pdf


My interpretation of this is that the initial clock priority is low,
so CPOL=0. The rising edge will be the leading edge, so CPHA=0. So
that makes the mode = 0.


Cheers, Pieter





[Index of Archives]     [Linux Kernel]     [Linux ARM (vger)]     [Linux ARM MSM]     [Linux Omap]     [Linux Arm]     [Linux Tegra]     [Fedora ARM]     [Linux for Samsung SOC]     [eCos]     [Linux Fastboot]     [Gcc Help]     [Git]     [DCCP]     [IETF Announce]     [Security]     [Linux MIPS]     [Yosemite Campsites]

  Powered by Linux