Re: KSZ8795 not detected at start to boot from NFS

[Andrew Lunn <andrew@xxxxxxx>]

On Sun, Jan 05, 2025 at 05:33:38PM +0100, Jörg Sommer wrote:
> Hi everyone,
> 
> I've added you to the list of recipients, because you where somehow involved
> in changes of the KSZ-SPI switch code.
> 
> We are debating the SPI mode setting for the microchip ksz8795 and ksz9477
> and possibly others. Since the commit
> 8c4599f49841dd663402ec52325dc2233add1d32 the SPI mode gets fixed to mode 3
> in the code. But at least my ksz8795 works also with mode 0 and shows better
> initialization behaviour with mode 0.
> 
> The big question is: can both (or all ksz) chips work with both modes?
> Should this setting stay in code or moved to the device tree?
> 
> The specs are here, but I found no evidence about the supported/recommended
> SPI modes:
> 
> https://ww1.microchip.com/downloads/en/DeviceDoc/KSZ9563R-Data-Sheet-DS00002419D.pdf

Don't trust what i say, i'm not an SPI expert, but i can use grep.

https://www.kernel.org/doc/Documentation/spi/spi-summary says:


I'm confused.  What are these four SPI "clock modes"?
-----------------------------------------------------
It's easy to be confused here, and the vendor documentation you'll
find isn't necessarily helpful.  The four modes combine two mode bits:

 - CPOL indicates the initial clock polarity.  CPOL=0 means the
   clock starts low, so the first (leading) edge is rising, and
   the second (trailing) edge is falling.  CPOL=1 means the clock
   starts high, so the first (leading) edge is falling.

 - CPHA indicates the clock phase used to sample data; CPHA=0 says
   sample on the leading edge, CPHA=1 means the trailing edge.

   Since the signal needs to stablize before it's sampled, CPHA=0
   implies that its data is written half a clock before the first
   clock edge.  The chipselect may have made it become available.

Chip specs won't always say "uses SPI mode X" in as many words,
but their timing diagrams will make the CPOL and CPHA modes clear.

In the SPI mode number, CPOL is the high order bit and CPHA is the
low order bit.  So when a chip's timing diagram shows the clock
starting low (CPOL=0) and data stabilized for sampling during the
trailing clock edge (CPHA=1), that's SPI mode 1.

And in the datasheet it says:

  SCL is expected to stay low when SPI operation is idle.
  
  Input data on SDI is latched on the rising edge of serial clock
  SCL. Output data on SDO is clocked on the falling edge of SCL.

My interpretation of this is that the initial clock priority is low,
so CPOL=0. The rising edge will be the leading edge, so CPHA=0. So
that makes the mode = 0.

Can you hard code this in the driver? I guess that depends on if you
want to support a PCB that puts in a line driver which adds a NOT gate
to the clock?  Does that ever happen? I don't know. The real SPI
experts should answer that.

	Andrew