On Wed, Oct 09, 2024 at 09:12:02AM +0300, Mika Westerberg wrote: > From: Alexander Usyskin <alexander.usyskin@xxxxxxxxx> > > The manufacturing access to the PCH/SoC SPI device is traditionally > performed via userspace driver accessing registers via /dev/mem but due > to security concerns /dev/mem access is being much restricted, hence the > reason for utilizing dedicated Intel PCH/SoC SPI controller driver, > which is already implemented in the Linux kernel. > > Intel PCH/SoC SPI controller protects the flash storage via two > mechanisms one is the via region protection registers and second via > BIOS lock. The BIOS locks only the BIOS regions usually 0 and/or 6. > > The device always boots with BIOS lock set, but during manufacturing the > BIOS lock has to be lifted in order to enable the write access. This can > be done by passing "writeable=1" in the command line when the driver is > loaded. This "locked" state is exposed through new sysfs attributes > (intel_spi_locked, intel_spi_bios_locked). > > Second, also the region protection status is exposed via sysfs attribute > (intel_spi_protected) as the manufacturing will need the both files in > order to validate that the device is properly sealed. > > Includes code written by Tamar Mashiah. > > Signed-off-by: Alexander Usyskin <alexander.usyskin@xxxxxxxxx> > Co-developed-by: Tomas Winkler <tomas.winkler@xxxxxxxxx> > Signed-off-by: Tomas Winkler <tomas.winkler@xxxxxxxxx> Just learned that Tomas just left Intel so this address is not working anymore, I'll resend with that updated.