Re: Add stacked and parallel memories support in spi-nor

[Miquel Raynal <miquel.raynal@xxxxxxxxxxx>]

Hi Amit,

> For implementing this the current DT binding[1] [2] [3] need to be updated as follows.
> 
> 
> 
> stacked-memories DT changes:
> 
> - Flash size information can be retrieved directly from the flash, so it has been removed from the DT binding.
> 
> - Each stacked flash will have its own flash node. This approach allows flashes of different makes and sizes to be stacked together, as each flash will be probed individually.
> 
> -  Each of the flash node will have its own "reg" property that will contain its physical CS.

These three first points are just describing the existing bindings for
non-concatenated situations.

> - The stacked-memories DT bindings will contain the phandles of the flash nodes connected in stacked mode.
> 
> - The first flash node will contain the mtd partition that would have the cross over memory staring at a memory location in the first flash and ending at some memory location of the 2nd flash

I don't like that much. Describing partitions past the actual device
sounds wrong. If you look into [1] there is a suggestion from Rob to
handle this case using a property that tells us there is a
continuation, so from a software perspective we can easily make the
link, but on the hardware description side the information are correct.

If this description is accepted, then fine, you can deprecate the 
"stacked-memories" property.

>  - The new layer will update the mtd->size and other mtd_info parameters after both the flashes are probed and will call mtd_device_register with the combined information.

Okay, this is back to the mtd-concat thing I initially proposed, but I
believe it can work.

[...]

> parallel-memories DT changes:
> 
> - Flash size information can be retrieved directly from the flash, so it has been removed from the DT binding.

It's not really about the size but more about the fact that two
memories are in use. If the stacked situation does not require anything
specific besides the partitions trick, then you can assume that double
reg flashes are just two flashes and this can be your way to
discriminate the data organization. But I don't like much this shortcut
because it is not future proof, and instead I'd keep the stacked-memory
property. If you don't like the size, I don't really care, just use it
as a boolean. But I believe we need some naming to tell the OS that the
data is spread in a specific way inside the memory devices.

> - Each flash connected in parallel mode should be identical and will have one flash node for both the flash devices.

This is already the case.

> - The "reg" prop will contain the physical CS number for both the connected flashes.

This is already the case.

> - The new layer will double the mtd-> size and register it with the mtd layer.

This is not a DT change.


Thanks,
Miquèl