On Thu, Oct 26, 2023 at 05:23:02PM +0200, Eberhard Stoll wrote: > From: Eberhard Stoll <eberhard.stoll@xxxxxxxxxx> > > For spi devices the master clock output defines the sampling point > for receive data input stream (rising or falling edge). The receive > data stream from the device is delayed in relation to the master > clock output. > > For some devices this delay is larger than one half clock period, > which is normally the sampling point for receive data. In this case > receive data is sampled too early and the device fails to operate. > In consequence the spi clock has to be reduced to match the delay > characteristics and this reduces performance and is therefore not > recommended. > > Some spi controllers implement a 'clock to receive data delay' > compensation which shifts the receive sampling point. So we need > a property to set this value for each spi device. > > Add a parameter 'rx_sample_delay_ns' to enable setting the clock > to rx data delay for each spi device separately. > > The 'clock to receive data delay' value is often referenced as tCLQV > in spi device data sheets. This makes sense to me. We should probably also have core support which will constrain the clock rate such that we satisfy the timing constraint if the controller can't control this, that'd need a flag to let the core know that the controller has that ability. Could you send an incremental patch doing that please?
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