Re: [PATCH] spi: fsl-dspi: avoid SCK glitches with continuous transfers

[Mark Brown <broonie@xxxxxxxxxx>]

On Tue, 30 May 2023 01:34:02 +0300, Vladimir Oltean wrote:
> The DSPI controller has configurable timing for
> 
> (a) tCSC: the interval between the assertion of the chip select and the
>     first clock edge
> 
> (b) tASC: the interval between the last clock edge and the deassertion
>     of the chip select
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: fsl-dspi: avoid SCK glitches with continuous transfers
      commit: c5c31fb71f16ba75bad4ade208abbae225305b65

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark