Hi Mark, On Tue, May 30, 2023 at 01:34:02AM +0300, Vladimir Oltean wrote: > In other words, the default values (of 0 and 0 ns) result in SCK > glitches where the SCK transition to the idle state, as well as the SCK > transition from the idle state, will have no delay in between, and it > may appear that a SCK cycle has simply gone missing. The resulting > timing violation might cause data corruption in many peripherals, as > their chip select is asserted. I know you don't appreciate content-free pings, but is this patch on your radar? Thanks, Vladimir