Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Doug Anderson <dianders@xxxxxxxxxxxx>]

Hi,

On Tue, Apr 25, 2023 at 1:42 AM Vijaya Krishna Nivarthi
<quic_vnivarth@xxxxxxxxxxx> wrote:
>
> The CS_TOGGLE bit when set is supposed to instruct FW to
> toggle CS line between words. The driver with intent of
> disabling this behaviour has been unsetting BIT(0). This has
> not caused any trouble so far because the original BIT(1)
> is untouched and BIT(0) likely wasn't being used.
>
> Correct this to prevent a potential future bug.
>
> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@xxxxxxxxxxx>
> ---
>  drivers/spi/spi-geni-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> index ba7be50..8a7d1c2 100644
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c
> @@ -35,7 +35,7 @@
>  #define CS_DEMUX_OUTPUT_SEL    GENMASK(3, 0)
>
>  #define SE_SPI_TRANS_CFG       0x25c
> -#define CS_TOGGLE              BIT(0)
> +#define CS_TOGGLE              BIT(1)

Looks right to me from the datasheet I have access to. It's definitely
specified in an odd way on the datasheet, which lists bit 1 as this,
bit 2 and 3 as reserved, but bit 0 is absent. ...but seems like this
is really supposed to be 1.

I guess this never mattered because all we ever did was clear the bit
at init time and it must have already been cleared? ...and, of course,
on many Chromebooks we moved to just using a GPIO...

Fixes: 561de45f72bd ("spi: spi-geni-qcom: Add SPI driver support for
GENI based QUP")
Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>