Re: [PATCH] spi: Replace `dummy.nbytes` with `dummy.ncycles`

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On 09.03.2023 15:33, Michael Walle wrote:
The controllers that can talk in dummy ncycles don't need the
dummy.{buswidth, dtr} fields.

The controllers that can't talk in dummy cycles, but only on a "byte"
boundary need both buswidth and dtr fields. Assume a flash needs 32
dummy cycles for an op on 8D-8D-8D mode. If the controller does not have the buswidth and dtr info, it can't convert the dummy ncycles to nbytes. If he knows only that buswidth is 8, it will convert ncycles to 4 bytes.
If dtr is also specified it converts ncycles to 2 bytes.

No they don't need it. Lets take your semper flash and assume it needs
12 latency cycles. SPI-NOR will set ncycles to 12 *regardless of the mode or dtr setting*. The controller then knows we need 12 clock cycles. It has
then to figure out how that can be achieved. E.g. if it can only do the
"old" byte programming and is in quad mode, good for it. It will send 6
dummy bytes, which will result in 12 dummy clock cycles, because 1 byte
takes two clock cycles in quad SDR mode. If its in octal mode, send 12
bytes. If its in dual mode, send 3 bytes. Obiously, it cannot be in
single bit mode, because it cannot send 1.5 bytes..

You miss the fact that you can have 1-1-4. What buswidth do you use
for dummy, the address buswidth or the data buswidth?

Doesn't matter, does it? The driver is free to chose, 1, 4, or anything
else. You don't sample any data during the dummy phase.
To answer your question: single for instruction, single for address,
whatever you choose for dummy as long as there are ncycles space between
address and data, and quad for data.

Huh? How does the controller chose, based on what?

Depending on the capabilites of the hardware it will likely be 1 or 4.

What happens if crazy protocols like 1S-1S-8D appear? What buswidth
and transfer mode are you going to use for dummy?

Also doesn't matter. What matters is how many dummy clock cycles you
do. Again, they don't depent on the mode. You just have to count
the clock cycles between the address and the data phase (and that is
what your ncycle parameter will tell the controller).

And please don't tell me that "we're going to assume that
dummy.buswidth = address.buswidth because that's what we currently do
in SPI NOR", because I'm not convinced that the assumption is correct.

No, it doesn't matter :)


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