Re: Looking for a solution for CPM FSL SPI driver that swaps 16 bits words

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Le 07/03/2023 à 19:35, Mark Brown a écrit :
> On Tue, Mar 07, 2023 at 06:21:36PM +0000, Christophe Leroy wrote:
>>
>> On powerpc CPM soc, SPI handles words in reversed byte order. Therefore
>> when some drivers like the GPIO max7301 driver request 16 bits data,
>> data is sent in wrong byte order.
> 
> Clearly if the device is byte swapping the data incorrectly then you'll
> need to do an extra swap in the CPU before sending to the device, or get
> the DMA controller to do it if that's a feature it has, when using the
> 16 bit mode.
> 
>> We could do as in spi-fsl-spi.c SPI driver for the QE soc and force 8
>> bits transfer at all time:
> 
> Right, that's the simplest thing.

Yes it is for the general case, but I need to be able to continue using 
that reverting 16 bits mode for some special cases like my FPGA loader.

> 
>> What could be the best solution to force 8 bits transfer on generic
>> drivers like GPIO max7301 while still allowing aware drivers like my
>> FPGA loader to use 16 bits mode by reversing words by itself ?
> 
> If your FPGA loader is already reversing words you may as well just move
> it into the controller driver.

Well, my loader reverts words "in place" because it is the one who has 
allocated and prepared the DMA buffer. But if we move that swaping into 
the SPI controller driver, it won't be possible to do it "in place" 
because the controller cannot know it the caller plans to re-use data 
after. And I'm not sure about the performance if we start having the 
controler to start kmallocing new DMA buffers on the fly.

What about a new flag at SPI device registration to tell the SPI 
subsystem that this SPI device driver wants "raw/native 16 bits" data 
being sent as-is, that my loader would set in order to tell the 
controler "I have prepared the data, send it in your native 16 bits 
order mode" ?
And for all devices not setting that flags, the controller would 
fallback to 8 bits mode.

Thanks
Christophe




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