Looking for a solution for CPM FSL SPI driver that swaps 16 bits words

[Christophe Leroy <christophe.leroy@xxxxxxxxxx>]

Hello,

I'm wondering how to solve the following issue:

On powerpc CPM soc, SPI handles words in reversed byte order. Therefore 
when some drivers like the GPIO max7301 driver request 16 bits data, 
data is sent in wrong byte order.

$ git grep bits_per_word gpio-max7301.c
gpio-max7301.c: /* bits_per_word cannot be configured in platform data */
gpio-max7301.c:         spi->bits_per_word = 16;

We could do as in spi-fsl-spi.c SPI driver for the QE soc and force 8 
bits transfer at all time:

static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
				struct spi_device *spi,
				int bits_per_word)
{
	/* QE uses Little Endian for words > 8
	 * so transform all words > 8 into 8 bits
	 * Unfortnatly that doesn't work for LSB so
	 * reject these for now */
	/* Note: 32 bits word, LSB works iff
	 * tfcr/rfcr is set to CPMFCR_GBL */
	if (spi->mode & SPI_LSB_FIRST &&
	    bits_per_word > 8)
		return -EINVAL;
	if (bits_per_word > 8)
		return 8; /* pretend its 8 bits */
	return bits_per_word;
}



But this would be a pitty because 8 bits mode is far less efficient and 
requires much lower transfer speed on powerpc CPM soc.

I have some (out of tree for now) driver that is used to load a FPGA 
through SPI and has to transfer as much as 300 kbytes data. That driver 
knows that words have to be submitted in reversed byte order and is able 
to use the SPI driver at full speed in 16 bits transfer mode, but when I 
use max7301 GPIO driver it is a problem.

What could be the best solution to force 8 bits transfer on generic 
drivers like GPIO max7301 while still allowing aware drivers like my 
FPGA loader to use 16 bits mode by reversing words by itself ?

Thanks
Christophe