Hello Han,
on my SoC (LS1021a), the QSPI clock is derived from the CPU clock
(cluster1)
and neither is controlled by the Linux kernel (afair) but by the RCW (or
U-Boot).
I could create a function to read the corresponding registers but I do
not know
where I should place this function and how I should call this function
in a
portable way in the QSPI module to convert the nanoseconds into delay
cycles.
I thought this would be a small and simple patch but I guess these
changes will
require quite some time with my knowledge level that I do not have right
now.
Thank you all for the review!
Best regards,
Mario
On 2023-01-17 22:05, han.xu wrote:
On 23/01/17 06:10PM, Krzysztof Kozlowski wrote:
On 17/01/2023 17:33, Mario Kicherer wrote:
> Hello,
>
> unfortunately, the rx-sample-delay-ns property does not fit here, as we
> can only delay
> the sampling point between zero and three "half cycles" (or edges), not
> by an arbitrary
> number of nanoseconds.
Why this is a problem for FSL but not for other platforms having
exactly
the same constraints/property?
Hi Mario,
Please use the common delay in DT and calculate to half cycle in
driver, we have
the similar discussion before for fspi controller delay settings.
Best regards,
Krzysztof
