On Wed, Aug 10, 2022 at 05:51:33PM +0200, Neil Armstrong wrote: > On 10/08/2022 16:49, Mark Brown wrote: > > I don't recall the code for clock providers being that hard? They're > > generally pretty small, some of the ASoC CODEC drivers did something > > similar. > Seems over-engineering to me, but I can explore this path if it's the best > route to follow. Please. > > > had an open-coded function which perfectly worked before. > > Except in the cases it didn't... > It did but wasn't generic enough to take the new clock path introduced > in the new SoCs. Right, it's leaving landmines lying around - it's hard for me to be confident that we couldn't also get another surprise due to a new test case exercising the code differently somehow, never mind the fragility of the code. > > > I'm perfectly OK to remove the CCF driver for the legacy clock path > > > and return back to the old open coded calculation since it perfectly > > > worked and stop using the legacy clock path for new SoCs since it would > > > never be selected anyway... > > It does seem better to go the clock provider route TBH. > I'm afraid this won't fix the problem since CCF won't set the clock again > if the rate is already ok in it's cache, we'd still need to save the divider > value and restore it after the reset as I did on this exact patch. The goal here is to ensure that the clock framework's idea of what the programmed configuration is and the SPI driver's idea of what that is can't get out of sync - instead of saving the value by virtue of reading it back out of the hardware at some specific point and hoping that there's never any changes triggered by the clock framework between the save and restore the driver is getting notified whenever there's a change being made and can update the cache then. That way we ensure we can't miss any cases and things are robust.
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