On 09/08/2022 17:27, Mark Brown wrote:
On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(),
this resets the SPICC_CONREG register and notably the value set by the
Common Clock Framework.
This saves the datarate dividor value between message to keep the last
set value by the Common Clock Framework.
When you say the value set by the clock framework does that mean that
the clock driver is adjusting hardware inside the SPI controller IP
block which is then getting reset by the SPI driver without the SPI
driver knowing about it? That seems like a bad idea as you're finding
here.
The SPI driver is explicitely triggering a reset at the end of each message
to get back to a clean HW state, but it does reset the content of the "legacy"
registers containing the power of 2 divider value, the new registers configuring
the new clock divider path (only on newer SoCs) doesn't get cleared.
This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
because we recalculated and wrote the rate for each xfer.
Note that the rate might change per transfer.
It's taken in account, this case is when the rate doesn't change.
