Re: spi-pl022 on lpc32xx

[Trevor Woerner <twoerner@xxxxxxxxx>]

Hi Vladimir,

This is great: I've now heard from the driver's maintainer, and the 2 other
people (other than me) still using this SoC ;-)

On Tue 2022-03-29 @ 09:59:07 PM, Vladimir Zapolskiy wrote:
> FWIW on my board I do use both SSP0 and SSP1 at once, but I didn't rebase
> the dts/kernel for a long time, so the examples might be outdated:
> 
> &ssp0 {
> 	num-cs = <1>;
> 	cs-gpios = <&gpio 3 5 GPIO_ACTIVE_HIGH>; /* SSEL0 */
> 
> 	sc16is752@0 {
> 		compatible = "nxp,sc16is752";
> 		reg = <0>;
> 		spi-max-frequency = <4000000>;
> 
> 		/* 18.432 MHz external oscillator */
> 		clocks = <&xtal_18432k>;
> 
> 		/* Interrupt to GPI_07 */
> 		interrupt-parent = <&sic2>;
> 		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
> 	};
> };
> 
> &ssp1 {
> 	num-cs = <1>;
> 	cs-gpios = <&gpio 3 4 GPIO_ACTIVE_HIGH>;

The chip selects of most SPI devices are active low (and the s25fl216k is
no exception), so *technically* this should probably be GPIO_ACTIVE_LOW.
Regardless, the spi-pl022 driver ignores this parameter anyway:
	https://elixir.bootlin.com/linux/v5.17.1/source/drivers/spi/spi-pl022.c#L458

> 	s25fl216k@0 {
> 		compatible = "s25fl216k", "jedec,spi-nor";
> 		reg = <0>;
> 		spi-max-frequency = <150000>;
> 		spi-cpol;
> 		spi-cpha;
> 	};
> };
> 
> Also SSP0 is enabled on PhyTec phy3250 board, there is an at25 eeprom on it,
> I've just briefly checked the device tree node, and apparently it contains
> some references/properties specific to the PL022 SPI driver.

Thanks for the report. Both you and Alexander are using SSP on this SoC
successfully, and it looks like your configurations are pretty much what I'm
using.

That means it's not the driver, and it's probably not my dts. I'm getting the
feeling that I'm being messed up by my 1st stage bootloader which is
configuring SPI and then leaving it running. I noticed that my SPI_CTRL
register is still setup with the SPI clocks running. Simply disabling the SPI
clocks on startup, however, doesn't seem to fix things. So then I started
looking at the various pinmuxing registers and noticed that nothing is setup
for SSP. The pins that are muxed for SSP are all left in their default
configurations on my device (which means they're all setup for SPI since SPI
is the default and SSP is the alternate).

Any chance either your or Alexander know what register 0x4002_8108 contains?
Maybe you have devmem2 available? Maybe you have bootloaders that are setting
up the pinmuxing for SSP mode for you?

The docs talk about how to configure SPI, and how to configure SSP. But they
don't talk about how to turn one off and enable the other (or if that's even
possible). If it's not possible for this SoC to switch between the two, then
my only option would be to write an SPI driver.

Best regards,
	Trevor