Re: [PATCH v2 2/2] spi: fsl-spi: Implement trailing bits

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On Mon, Feb 28, 2022 at 04:02:30PM +0000, Christophe Leroy wrote:
> Le 28/02/2022 à 16:29, Mark Brown a écrit :

> > The binding looks good now but this is still driver specific code when
> > it looks like it could easily be implemented in the core - like I said
> > on the previous version you'd need to update drivers to advertise less
> > than 8 bits but there's basically nothing driver specific I can see here
> > so any driver using transfer_one() would get support that way.

> Argh ! Sorry your comment to the previous version ended up in Junk 
> mails. I see it now.

No problem.

> We discussed that back in 2016 in 
> https://lore.kernel.org/linux-spi/20160824112701.GE22076@xxxxxxxxxxxxx/ 
> and my understanding at that time was that it was not something that 
> could be done at core level.

> But maybe things have changed since then ?

What I said then was "it would need a new core feature" which is what
the binding does, I'm suggesting that you also do that for the handling
of the implementation as well.

Actually now I think about it perhaps this shouldn't be a binding at all
but rather something specified by the client driver - presumably any
system using an affected device is going to need these extra clock
cycles so they'll all need to add the same property.

> By the way, fsl-spi driver doesn't implement transfer_one() but 
> transfer_one_message() so it takes care of the chipselect changes and 
> therefore the final dummy transfer with CS off is to be done there as 
> far as I understand.

> Would it mean changing fsl-spi driver to implement transfer_one() first ?

Well, if it can implement transfer_one() without any negative
consequences whichh

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