I've tried different combinations of GPIO_ACTIVE_HIGH/LOW. I modified the ar9134x-spi.c driver to allow gpiod descriptors. I've tried creating a virtual CS of 3, using cs-gpios. Nothing seems to work and all I get are JEDEC IDs of 0's. Is there something I else I am missing here? For reference, this is a Carambola 2 module on a custom board, with an extra SPI 32Mb chip on GPIO11, which is not "HW" chip select pin. On Thu, Nov 4, 2021 at 11:20 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Dave, > > On Thu, Nov 4, 2021 at 3:58 PM Dave Bender <codehero@xxxxxxxxx> wrote: > > On Thu, Nov 4, 2021 at 5:50 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > > Does it work if you change GPIO_ACTIVE_LOW to GPIO_ACTIVE_HIGH? > > > > There is a pullup resistor on that CS line, so that GPIO must be active low. > > I do believe you. But there's been some issues with inverted CS > gpio behavior when switching from board files to DT, so I thought > I'd better ask to try... > > > Digging deeper into the code, it looks like David Bauer made some > > changes that limit the spi driver's CS usage to only the CS0, CS1, CS2 > > pins. > > There is also no bounds checking on the CS value. > > I don't understand how this driver can even use generic GPIO if it > > forces use of the CS bits on the SPI_IOC register. > > OK, that sounds like a reasonable culprit... > > > > > static int ar934x_spi_transfer_one_message(struct spi_controller *master, > > struct spi_message *m) > > { > > .... > > .... > > for (trx_done = 0; trx_done < t->len; trx_done += 4) { > > > > ..... > > reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term, > > trx_cur * 8); > > iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL); > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds