Re: [PATCH 2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI

[Rob Herring <robh@xxxxxxxxxx>]

On Fri, 24 Sep 2021 15:37:09 +0530, Sai Krishna Potthuri wrote:
> Add new compatible to support Cadence Octal SPI(OSPI) controller on
> Xilinx Versal SoCs, also add power-domains property to the properties
> list and marked as required for Xilinx Versal OSPI compatible.
> 
> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xxxxxxxxxx>
> ---
>  .../devicetree/bindings/spi/cdns,qspi-nor.yaml       | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1532183


spi@ff705000: resets: [[6, 37]] is too short
	arch/arm/boot/dts/socfpga_arria5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dt.yaml
	arch/arm/boot/dts/socfpga_vt.dt.yaml