Re: [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling

["Nandan, Apurva" <a-nandan@xxxxxx>]

On 13-Jul-21 11:55 PM, Mark Brown wrote:
> On Tue, Jul 13, 2021 at 12:57:41PM +0000, Apurva Nandan wrote:
> 
>> cadence-quadspi controller doesn't allow an address phase when
>> auto-polling the busy bit on the status register. Unlike SPI NOR
>> flashes, SPI NAND flashes do require the address of status register
>> when polling the busy bit using the read register operation. As
>> Auto-HW polling is enabled by default, cadence-quadspi returns a
>> timeout for every write operation after an indefinite amount of
>> polling on SPI NAND flashes.
> 
>> Disable Auto-HW polling completely as the spi-nor core, spinand core,
>> etc. take care of polling the busy bit on their own.
> 
> Would it not be better to only disable this on NAND rather than
> disabling it completely?
> 

I am not sure how it is possible currently in the controller, could you
please suggest a way? Also, should we have this logic of checking flash
device type in the cadence-quadspi controller? SPI controller should be
generic to all flash cores right?

In my opinion, it shouldn't harm as spi-nor core doesn't depend on HW
polling anyways and auto-HW polling is a minor overhead.

Regards,
Apurva Nandan