On Tue, Jul 13, 2021 at 12:57:41PM +0000, Apurva Nandan wrote: > cadence-quadspi controller doesn't allow an address phase when > auto-polling the busy bit on the status register. Unlike SPI NOR > flashes, SPI NAND flashes do require the address of status register > when polling the busy bit using the read register operation. As > Auto-HW polling is enabled by default, cadence-quadspi returns a > timeout for every write operation after an indefinite amount of > polling on SPI NAND flashes. > Disable Auto-HW polling completely as the spi-nor core, spinand core, > etc. take care of polling the busy bit on their own. Would it not be better to only disable this on NAND rather than disabling it completely?
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