On 01/06/21 02:47PM, Michael Walle wrote: > Am 2021-05-31 20:17, schrieb Pratyush Yadav: > > The Octal DTR configuration is stored in the CFR5V register. This > > register is 1 byte wide. But 1 byte long transactions are not allowed in > > 8D-8D-8D mode. Since the next byte address does not contain any > > register, it is safe to write any value to it. Write a 0 to it. > > > > Signed-off-by: Pratyush Yadav <p.yadav@xxxxxx> > > --- > > Can't say much, because there is no public datasheet, is there? https://www.cypress.com/file/513996/download > > But looks sane. Same for patch 3/6. -- Regards, Pratyush Yadav Texas Instruments Inc.