On 07/05/21 04:48PM, Mark Brown wrote: > On Fri, May 07, 2021 at 12:48:27AM +0530, Pratyush Yadav wrote: > > In 8D-8D-8D mode two bytes are transferred per cycle. So an odd number > > of bytes cannot be transferred because it would leave a residual half > > cycle at the end. Consider such a transfer invalid and reject it. > > Reviwed-by: Mark Brown <broonie@xxxxxxxxxx> Thanks. BTW, s/Reviwed/Reviewed/. -- Regards, Pratyush Yadav Texas Instruments Inc.
Re: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
- Subject: Re: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
- From: Pratyush Yadav <p.yadav@xxxxxx>
- Date: Fri, 7 May 2021 22:19:14 +0530
- Cc: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>, Michael Walle <michael@xxxxxxxx>, Miquel Raynal <miquel.raynal@xxxxxxxxxxx>, Richard Weinberger <richard@xxxxxx>, Vignesh Raghavendra <vigneshr@xxxxxx>, <linux-mtd@xxxxxxxxxxxxxxxxxxx>, <linux-kernel@xxxxxxxxxxxxxxx>, <linux-spi@xxxxxxxxxxxxxxx>
- In-reply-to: <20210507154825.GE6383@sirena.org.uk>
- References: <20210506191829.8271-1-p.yadav@ti.com> <20210506191829.8271-5-p.yadav@ti.com> <20210507154825.GE6383@sirena.org.uk>
- User-agent: NeoMutt/20171215
- References:
- [PATCH 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode.
- From: Pratyush Yadav
- [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
- From: Pratyush Yadav
- Re: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
- From: Mark Brown
- [PATCH 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode.
- Prev by Date: [PATCH] spi: tegra210-quad: Fix an error message
- Next by Date: Re: [PATCH 6/6] mtd: spi-nor: core; avoid odd length/address writes in 8D-8D-8D mode
- Previous by thread: Re: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
- Next by thread: [PATCH 5/6] mtd: spi-nor: core; avoid odd length/address reads on 8D-8D-8D mode
- Index(es):
 |