Re: [PATCH v3 02/21] spi: dw: Add DWC SSI capability

[Andy Shevchenko <andy.shevchenko@xxxxxxxxx>]

On Fri, Oct 02, 2020 at 01:28:10AM +0300, Serge Semin wrote:
> Currently DWC SSI core is supported by means of setting up the
> core-specific update_cr0() callback. It isn't suitable for multiple
> reasons. First of all having exported several methods doing the same thing
> but for different chips makes the code harder to maintain. Secondly the
> spi-dw-core driver exports the methods, then the spi-dw-mmio driver sets
> the private data callback with one of them so to be called by the core
> driver again. That makes the code logic too complicated. Thirdly using
> callbacks for just updating the CR0 register is problematic, since in case
> if the register needed to be updated from different parts of the code,
> we'd have to create another callback (for instance the SPI device-specific
> parameters don't need to be calculated each time the SPI transfer is
> submitted, so it's better to pre-calculate the CR0 data at the SPI-device
> setup stage).
> 
> So keeping all the above in mind let's discard the update_cr0() callbacks,
> define a generic and static dw_spi_update_cr0() method and create the
> DW_SPI_CAP_DWC_SSI capability, which when enabled would activate the
> alternative CR0 register layout.
> 
> While at it add the comments to the code path of the normal DW APB SSI
> controller setup to make the dw_spi_update_cr0() method looking coherent.

What the point to increase indentation level and produce additional churn?
Can't you simply leave functions, unexport them, and call in one conditional of
whatever new function is called?

I have an impression that split of the series is done in a way that first
patches in the series are not optimized to what is done in the last patches in
the series.

-- 
With Best Regards,
Andy Shevchenko