Hi Vignesh,
Thank you for the review comments and suggestions.
On 17/9/2019 12:50 AM, Vignesh Raghavendra wrote:
Hi,
On 16/09/19 1:08 PM, Ramuthevar,Vadivel MuruganX wrote:
patch 1: Add YAML for cadence-qspi devicetree cdocumentation.
patch 2: cadence-qspi controller driver to support QSPI-NAND flash
using existing spi-nand framework with legacy spi protocol.
Nope, you cannot have two drivers for the same IP (i.e Cadence QSPI)
just to support to different types of SPI memories. This is the reason
why spi_mem_ops was introduced.
Please rewrite this driver over to use spi_mem_ops (instead of using
generic SPI xfers) so that same driver supports both SPI-NOR and
SPI-NAND flashes. Once that's done drivers/mtd/spi-nor/cadence-quadspi.c
can be deleted.
There are few existing examples of spi_mem_ops users in drivers/spi/
(git grep spi_mem_ops) and materials here on how to write such a driver:
[1]
https://bootlin.com/blog/spi-mem-bringing-some-consistency-to-the-spi-memory-ecosystem/
[2] https://www.youtube.com/watch?v=PkWbuLM_gmU
Agreed!, Surely let me go through the above link and put my effort to
rewrite the drivers as per your suggestions.
---
With Best Regards
Vadivel Murugan R
Ramuthevar Vadivel Murugan (2):
dt-bindings: spi: Add support for cadence-qspi IP Intel LGM SoC
spi: cadence-qspi: Add QSPI support for Intel LGM SoC
.../devicetree/bindings/spi/cadence,qspi-nand.yaml | 84 +++
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-cadence-qspi-apb.c | 644 +++++++++++++++++++++
drivers/spi/spi-cadence-qspi-apb.h | 174 ++++++
drivers/spi/spi-cadence-qspi.c | 461 +++++++++++++++
drivers/spi/spi-cadence-qspi.h | 73 +++
7 files changed, 1446 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/cadence,qspi-nand.yaml
create mode 100644 drivers/spi/spi-cadence-qspi-apb.c
create mode 100644 drivers/spi/spi-cadence-qspi-apb.h
create mode 100644 drivers/spi/spi-cadence-qspi.c
create mode 100644 drivers/spi/spi-cadence-qspi.h
