Re: [PATCH 1/4] spi: core: Allow both TX and RX transfers in 3WIRE

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On Wed, Sep 05, 2018 at 03:09:42PM +0200, Linus Walleij wrote:
> On Wed, Sep 5, 2018 at 11:39 AM Mark Brown <broonie@xxxxxxxxxx> wrote:

> > AFAICT from the rest of the series the root cause here is that you're
> > trying to work around the GPIO controller setting the wrong flags rather
> > than an actual fix here - there's no need for any change that I can see.

> I think that may be up to the interpretation of
> SPI_[MASTER|CONTROLLER]_NO_[RX|TX] flags.

> From the code and the bitbanging inlines it is clear that
> the actual semantics of these flags are:
> SPI_MASTER_NO_RX == does not have a MISO line
> SPI_MASTER_NO_TX == does not have a MOSI line

I would be very surprised if whoever wrote the DT parsing code in the
bitbanging driver even considered the three wire case.  That's clearly
not a sensible reading of NO_[RT]X from a natural langauge point of
view.

> Maybe I should make a patch renaming the flags
> as SPI_*_NO_MISO, SPI_*_NO_MOSI
> as that is how they are used in the code.

That's how they're used in that specific bit of code, it's certainly not
how the validation code which I wrote uses them, and I'm not convinced
that it's a particularly useful thing to tell the rest of the world
about - users will care if they can do the operation, it's not *super*
important to them which wires it uses to do that.

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