Re: [PATCH 1/4] spi: core: Allow both TX and RX transfers in 3WIRE

[Linus Walleij <linus.walleij@xxxxxxxxxx>]

On Wed, Sep 5, 2018 at 11:39 AM Mark Brown <broonie@xxxxxxxxxx> wrote:
> On Tue, Sep 04, 2018 at 10:47:14PM +0200, Linus Walleij wrote:
>
> > But it's confusing and fragile, I've heard this way of coding has
> > a name (probably not a pretty one) and should be avoided. Geert
> > had a better idea on how to do it so I rewrote it in a cleaner way.
>
> AFAICT from the rest of the series the root cause here is that you're
> trying to work around the GPIO controller setting the wrong flags rather
> than an actual fix here - there's no need for any change that I can see.

I think that may be up to the interpretation of
SPI_[MASTER|CONTROLLER]_NO_[RX|TX] flags.

>From the code and the bitbanging inlines it is clear that
the actual semantics of these flags are:
SPI_MASTER_NO_RX == does not have a MISO line
SPI_MASTER_NO_TX == does not have a MOSI line

But these names are pretty confusing, since a 3WIRE
only has a single line (MISO) but can do both RX and
TX transfers.

Maybe I should make a patch renaming the flags
as SPI_*_NO_MISO, SPI_*_NO_MOSI
as that is how they are used in the code.

Yours,
Linus Walleij