On sobota 11. srpna 2018 13:49:43 CEST, Kosta Zertsekel wrote:
SPI direct write
============
Say, we want to write a huge binary image to FPGA connected via SPI bus.
So, we need to configure MBUS memory window to forward writes/stores
to SPI controller.
Say, <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000> for SPI0-DEV1.
Hence, in `orion_spi_probe` the code will set
`direct_access.vaddr = 0xf1100000`
and `direct_access.size = PAGE_SIZE`.
And then, some time later, `orion_spi_write_read` is called with huge
`xfer->tx_buf` and `xfer->len`.
Now, `iowrite32_rep` comes into play and does a peta-zillion four-byte
writes/stores to
the ***same*** address 0xf1100000. And SPI controller forwards every
four-byte write
via shift-out register.
Does it all sound correct?
Hi Kosta,
I do not think that this is correct, but I have no experience with the
direct mode (I thought that I used it some time ago, but I was wrong; I
also don't know how MBUS works). All I know comes from a file called
"A38x-Functional-Spec-PU0A.pdf" [1]. There is some description on pages 270
and 271.
At least on A38x, the SPI direct mode is limited to 32 bytes for both reads
and writes. There are also some semi-flexible headres to be prepended to
the exchanged data. It looks like something intended for flash access.
Hope this helps,
Jan
[1]
http://www.marvell.com/embedded-processors/armada-38x/assets/A38x-Functional-Spec-PU0A.pdf
