Understanding Marvell SPI direct read/write mode

[Kosta Zertsekel <zertsekel@xxxxxxxxx>]

Hi guys,

I'm trying to understand SPI direct read/write of Marvell SPI
controller (spi-orion.c).

SPI direct write
============
Say, we want to write a huge binary image to FPGA connected via SPI bus.
So, we need to configure MBUS memory window to forward writes/stores
to SPI controller.
Say, <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000> for SPI0-DEV1.
Hence, in `orion_spi_probe` the code will set `direct_access.vaddr = 0xf1100000`
and `direct_access.size = PAGE_SIZE`.
And then, some time later, `orion_spi_write_read` is called with huge
`xfer->tx_buf` and `xfer->len`.
Now, `iowrite32_rep` comes into play and does a peta-zillion four-byte
writes/stores to
the ***same*** address 0xf1100000. And SPI controller forwards every
four-byte write
via shift-out register.
Does it all sound correct?
Is it always enough to open a minimal memory window of 64K on MBUS and
minimal MMU mapping of PAGE_SIZE?

SPI direct read
============
Same MBUS, `vaddr` and `size` configuration as above.
But now `orion_spi_write_read` is called to read a huge binary image from FPGA.
I know that direct read access is not implemented, but let's assume the code is:
```
orion_spi_write_read()
{
        ...
        count = xfer->len;
        vaddr = orion_spi->child[cs].direct_access.vaddr;
        if (vaddr && xfer->rx_buf && word_len == 8) {
                unsigned int cnt = count / 4;
                ioread32_rep(vaddr, xfer->rx_buf, cnt);
                return count;
        }
        ...
}
```
So, does it all seem correct?
Does SPI controller forwards the content of `SPI Data In Register` back to CPU?

Thanks,
--- Kosta Z.