On Thu, Aug 02, 2018 at 07:27:45PM +0000, Trent Piepho wrote: > On Thu, 2018-08-02 at 10:07 +0800, masonccyang@xxxxxxxxxxx wrote: > > + mxic_spi_set_input_delay_dqs(mxic, 0xf); > > + ret = clk_set_phase(mxic->send_dly_clk, 360 / (1000000000 / freq)); > Can also be written as freq*9/25000000. > > + if (ret) > > + return ret; > > + > > + clk_prepare_enable(mxic->send_clk); > > + clk_prepare_enable(mxic->send_dly_clk); > > + > > + return 0; > Won't changing the clock rate in spi_setup break if there are two > slaves which use different rates? Gah, I missed that the rate is set by clk_set_phase() - the clk_set_rate() calls are setting constant values so they're fine. Yes, this is a bug.
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