[PATCH v4] spi: dw: round up result of calculation for clock divider

[Matthias Seidel <kernel@xxxxxxxxxxx>]

Avoid ending up with a higher frequency than requested

Signed-off-by: Matthias Seidel <kernel@xxxxxxxxxxx>
---
v4: Corrected subject, thanks for your work!

Previously failing example:
requested transfer freq: 16MHz
max_freq = 200MHz
calculated clk_div = 12
actual frequency = 200/12 = 16.6666MHz
---
 drivers/spi/spi-dw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index c85e4b3..27960e4 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -300,7 +300,7 @@ static int dw_spi_transfer_one(struct spi_master *master,
 	if (transfer->speed_hz != dws->current_freq) {
 		if (transfer->speed_hz != chip->speed_hz) {
 			/* clk_div doesn't support odd number */
-			chip->clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe;
+			chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 			chip->speed_hz = transfer->speed_hz;
 		}
 		dws->current_freq = transfer->speed_hz;
-- 
2.7.4



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