Re: [PATCH v2 2/2] spi: dw: round up result of calculation for clock divider

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On Sun, Sep 04, 2016 at 02:05:35AM +0200, Matthias Seidel wrote:

>  			/* clk_div doesn't support odd number */
> -			chip->clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe;
> +			chip->clk_div = ((dws->max_freq + transfer->speed_hz) /
> +				transfer->speed_hz + 1) & 0xfffe;

Can we not use DIV_ROUND_UP here if that's what we're trying to do?  The
above probably needs a comment if not, I'm finding the intent rather
confusing looking at the code.

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