On Wed, Aug 26, 2015 at 11:56:04AM +0530, Ranjit Waghmode wrote: > To support dual parallel mode operation of ZynqMP GQSPI controller > following API's are added inside the core: As covered in SubmittingPatches please try to make each patch a single change rather than having multiple separate changes in one commit. > + /* Controller may support more than one chip. > + * This flag will enable that feature. > + */ > +#define SPI_MASTER_BOTH_CS BIT(8) /* enable both chips */ This isn't saying that the controller supports more than one chip, it's saying that the controller supports asserting more than one chip select at once which isn't the same thing. I'm also not entirely sure that this makes sense as a separate feature to the data striping one - I'm struggling to think of a way to use this sensibly separately to that.
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