On Thu, Apr 09, 2015 at 11:31:12PM +0200, Bert Vermeulen wrote: > On 04/06/2015 06:39 PM, Mark Brown wrote:> On Mon, Apr 06, 2015 at > > I queried this on a previous version and asked for the code to be better > > documented... > I documented it in the commit message: I'm asking for the *code* to be better documented. Right now it's just raising obvious questions which are at best going to cost people time digging for the reasons. > The m25p80-compatible boot flash and (some models) MMC use regular SPI, > bitbanged as required by the SoC. However the SPI-connected CPLD has > a "fast write" mode, in which two bits are transferred by SPI clock > cycle. The second bit is transmitted with the SoC's CS2 pin. > Protocol drivers using this fast write facility signal this by setting > the cs_change flag on transfers. > The cs_change flag is used here instead of the openwrt version's > spi_transfer.fast_write flag. The CPLD driver sets this flag on a > per-transfer basis. No, this is broken - it's abusing a standard API in a way that's completly incompatible with the meaning of that API which is obviously a very bad idea, especially since good practice is to offload the implementation of that standard API to the core. It *sounds* like you're just trying to implement two wire mode which does have a standard API, please use that.
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