On 03/20/2015 01:51 PM, Mark Brown wrote: Mark, Thanks very much for your detailed review. I'll fix things according to your comments. However... > On Fri, Mar 20, 2015 at 01:16:32PM +0100, Bert Vermeulen wrote: >> +static void do_spi_byte(void __iomem *base, unsigned char byte) >> +{ >> + do_spi_clk(base, byte >> 7); >> + do_spi_clk(base, byte >> 6); >> + do_spi_clk(base, byte >> 5); >> + do_spi_clk(base, byte >> 4); >> + do_spi_clk(base, byte >> 3); >> + do_spi_clk(base, byte >> 2); >> + do_spi_clk(base, byte >> 1); >> + do_spi_clk(base, byte); > > This looks awfully like it's bitbanging the value out, can we not use > spi-bitbang here? > [...] >> +static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, >> + unsigned bit2) > > Why would we ever want the slow version? It is bitbanging, at least on write. The hardware has a shift register that is uses for reads. The generic spi for this board's architecture (ath79) indeed uses spi-bitbang. This "fast SPI" thing is what makes this one different: the boot flash and MMC use regular SPI on the same bus as the CPLD. This CPLD needs this fast SPI: a mode where it shifts in two bits per clock. The second bit is apparently sent via the CS2 pin. So I don't think spi-bitbang will do. I need to see about reworking things to use less custom queueing -- I'm not that familiar with this yet. -- Bert Vermeulen bert@xxxxxxxx email/xmpp -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html