Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:

> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.

> -	value &= ~SPI_CS_CONTROL_SW_MODE;
> +	orig = value &= ~SPI_CS_CONTROL_SW_MODE;
>  	writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
>  	value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
>  	if (value != orig) {

This is a *really* non-obvious fix, I'd have expected the original value
to be re-read from the hardware here rather than just tweaked, or at
least some comment explaining what's going on.  Possibly also saving to
a differently named temporary variable would do it but whatever I had to
go look at the context to figure out what was happening and even there I
was unclear.

Attachment: signature.asc
Description: Digital signature


[Index of Archives]     [Linux Kernel]     [Linux ARM (vger)]     [Linux ARM MSM]     [Linux Omap]     [Linux Arm]     [Linux Tegra]     [Fedora ARM]     [Linux for Samsung SOC]     [eCos]     [Linux Fastboot]     [Gcc Help]     [Git]     [DCCP]     [IETF Announce]     [Security]     [Linux MIPS]     [Yosemite Campsites]

  Powered by Linux