On Fri, Apr 18, 2014 at 12:26:07AM +0800, Chew Chiau Ee wrote: > From: Chew, Chiau Ee <chiau.ee.chew@xxxxxxxxx> > > Intel BayTrail PCI mode LPSS devices inclusive of SPI do not rely > on common clock framework. Thus, this patch allows the PCI mode > SPI host to pass the supported clock rate info to the core layer > which eventually used for speed calculation. As you mention we already have a clock API for passing around information about clocks, it would be much better to fix the fact that this isn't enabled on x86 than to add custom code to deal with clocks (even simple things like this) - this is far from the only place where it causes issues.
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