Hi,
On Mon, Jul 23, 2018 at 7:22 PM, Taniya Das <tdas@xxxxxxxxxxxxxx> wrote:
>
>
> On 7/24/2018 3:24 AM, Douglas Anderson wrote:
>>
>> Add both the interface and core clock.
>>
>> Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
>> ---
>>
>> Changes in v2:
>> - Only 19.2, 100, 150, and 300 MHz now.
>> - All clocks come from MAIN rather than EVEN.
>> - Use parent map 0 instead of new parent map 9.
>>
>> drivers/clk/qcom/gcc-sdm845.c | 63 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 63 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
>> index 0f694ed4238a..5bca634e277a 100644
>> --- a/drivers/clk/qcom/gcc-sdm845.c
>> +++ b/drivers/clk/qcom/gcc-sdm845.c
>> @@ -162,6 +162,13 @@ static const char * const gcc_parent_names_10[] = {
>> "core_bi_pll_test_se",
>> };
>> +static const char * const gcc_parent_names_9[] = {
>> + "bi_tcxo",
>> + "gpll0",
>> + "gpll0_out_even",
>> + "core_pi_sleep_clk",
>> +};
>> +
>
>
> Please remove this.
Oops, that's embarrassing. Please stay tuned for v3.
-Doug
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